Asic Verification Engineer Resume Sample
Andre Kuvalis
6346 Von Courts,
San Francisco,
CA
+1 (555) 590 0995
Work Experience
Senior Asic Verification Engineer
03/2018
-
PRESENT
Philadelphia, PA
- Prior verification experience in FPGA design/verification or other accelerated verification solution would be a good asset
- Extensive Verilog or VHDL design experience
- Experience with simulation, waveform, and other DV tools used in HW design
- Familiarity with scripting (csh, perl, awk, etc.)
- SystemC, Vera, and Specman are good assets
- Experience in industry standard mainstream video codecs like HEVC/H.264, VP codecs and extensions for video codecs would be a great asset
- An organized, enthusiastic self-starter with a passion for hardware verification methodologies
- Strong problem solving skills, and a keen attention to details
- Good interpersonal skills (verbal and written)
Asic Verification Engineer
01/2012
-
12/2017
Dallas, TX
- Capable of working both as an independent contributor and team member
- Willingness to work and mentor junior team members
- Develop verification test benches
- Timely execution of test plans
- Participate in, and assist in, FPGA emulation efforts
- Assist chip level design tradeoffs by working with design engineers
- Participate in review of design verification coding and coverage metrics
Co-op Asic Verification Engineer
06/2006
-
09/2011
Los Angeles, CA
- Experience with the latest ASIC verification methodologies, tools and scripting/programming languages
- Proven track record of a high level of innovation
- Self-motivation and the ability to execute effectively without supervision
- Understand and analyze RTL code coverage results
- Understand functional coverage methods
- Understand and develops system Verilog assertions
- Have efficient debugging and logic skills
- Familiarity with major simulation and debug tool vendors
- Power aware Verification, UVM-LP, UPF, and Dynamic Power Estimation
Education
International Technological University
2001 - 2005
Engineer's Degree in Electrical Engineering
Professional Skills
- Be a self-starter; possess excellent analytical and problem solving/debugging skills and have excellent verbal and written communication skills
- Strong Software Development Skills, OOP, AOP, Behavioral modeling, Scripting, and Automation skills
- Strong analytical/problem solving skills and pronounced attention to details
- Extremely strong programming skills including object-oriented programming
- Excellent communication skills and ability to work in a geographically diverse team environment
- Demonstrated experience designing in Verilog and/or System Verilog
- Prior Verification experience required
How to write Asic Verification Engineer Resume
Asic Verification Engineer role is responsible for programming, software, engineering, design, player, english, analytical, integration, database, java.
To write great resume for asic verification engineer job, your resume must include:
- Your contact information
- Work experience
- Education
- Skill listing
Contact Information For Asic Verification Engineer Resume
The section contact information is important in your asic verification engineer resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:
- First and last name
- Telephone number
Work Experience in Your Asic Verification Engineer Resume
The section work experience is an essential part of your asic verification engineer resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous asic verification engineer responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular asic verification engineer position you're applying to.
The work experience section should be the detailed summary of your latest 3 or 4 positions.
Representative Asic Verification Engineer resume experience can include:
- Prior experience debugging and validating memory subsystems is desirable
- Good debugging and problem-solving skills
- Prior Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies
- Proven leadership experience in verification
- Strong background and hands-on experience with verification environments, architecture definitions and development
- Team player with great interpersonal communication skills
Education on an Asic Verification Engineer Resume
Make sure to make education a priority on your asic verification engineer resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your asic verification engineer experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.
Additional details to include:
- School you graduated from
- Major/ minor
- Year of graduation
- Location of school
These are the four additional pieces of information you should mention when listing your education on your resume.
Professional Skills in Asic Verification Engineer Resume
When listing skills on your asic verification engineer resume, remember always to be honest about your level of ability. Include the Skills section after experience.
Present the most important skills in your resume, there's a list of typical asic verification engineer skills:
- Good communication skills, open and collaborative working style, team player
- Strong oral and written communication skills and the ability to document and present one’s work and status
- Very good communication skills and ability and desire to work in a geographically diverse team environment
- Experience: Basic digital design and programming experience desirable
- OOPs, C/C++ programming skills
- Industry experience with experience in development, integration & verification of ASIC & FPGA
List of Typical Experience For an Asic Verification Engineer Resume
1
Experience For Senior Asic Verification Engineer Resume
- Prior experience with high speed IOs like PCIE/USB/SATA is desirable
- Good hands on experience with cadence/Synopsys/Mentor tools
- Strong experience in verification of VLSI components, integrated circuitry, architectures and algorithms
- Working experience in IP/SoC verification using AMBA AXI, DMA, FIFO, etc modules
- Working experience in Simulation tools like Mentor Modelsim/Questasim, Synthesis tools, Coverage tools, and Regression tools
- Strong critical thinking, problem solving
- Fully experienced verification flow, including testplan, random driven test, coverage model, testbench, BFM modeling
- Definition, development and execution of ASIC/FPGA bring-up and validation plans
- Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies
2
Experience For Lead Asic Verification Engineer Resume
- Experience in developing UVM-based SV test-benches
- Experienced with defining block, sub-system or SOC top level test plans
- Extensive experience in developing UVM-based SV test-benches
- Highly experienced with defining block, sub-system and SOC top level test plans
- Perl and C/C++ programming language experience
- Experience of developing functional coverage code , coverage analysis
- Experience of developing verification environments is desirable
3
Experience For MTS Asic Verification Engineer Resume
- Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture
- Strong ASIC design Methodology
- Experience in digital design verification
- Verification work or research experience is an asset
- UVM verification experience highly desired
4
Experience For Principal Asic Verification Engineer Resume
- Experience in developing Constrained random tests for achieving Functional Coverage & Assertions based DV signoff
- Experience in pre-silicon RTL Verification
- BTech/ MTech with 1+ years of experience
- Unit/Sub-system/SOC level verification experience
- Hands-on experience with verification environments, architecture definitions and development
5
Experience For Co-op Asic Verification Engineer Resume
- ASIC/FPGA DV experience with UVM methodologies
- Relevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU sub-systems
- BS / MS with at least 8+ years of experience
- BS / MS with at least 5 years of experience
- Design verification experience (SystemVerilog or Verilog based)
- Experience with UVMf
- Experience in VLSI design, verification or implementation
- Developing and tracking of Verification plans
- Scripting - PERL, UNIX/LINUX, TCL
6
Experience For Senior. / MTS Asic Verification Engineer Resume
- Working with simulation environments based on VMM or UVM and possibly C
- Supporting regression runs (project dependent)
- Understanding and knowledge of verification methodologies, flows and quality metrics
- Understanding of software systems design tools and languages such as C and Python
- ASIC verification including writing verification test plans, verification environment development, behavioral model development and test case writing
- Contribute as an ASIC Verification Engineer developing the next generation of cloud, networking, and baseband processors
7
Experience For Asic Verification Engineer Resume
- Contribute as an ASIC Verification (Emulation) Engineer developing the next generation of cloud, networking, and baseband processors
- Object oriented programming and scripting is considered an asset
- Subject matter knowledge in major areas of responsibility. Growing breadth of understanding and a depth of specific expertise
- Develop SOC and block level Test benches, Verification Modeling, Test Plans, Test Cases, Responsible for verification strategies, and test generation schemes
- Verify internally developed RTL IP using 3rd party NVMe Verification IP
- Expertise in developing block level / system level verification environmen
- Knowledge of scripting languages like Perl, Tcl
8
Experience For Senior Asic Verification Engineer Resume
- Fluent in System Verilog and scripting languages such as Python or Perl
- Knowledge of System Verilog and scripting languages such as Python or Perl
- Think holistically: Apply leading edge verification methodologies
- Knowledge: Understanding of VHDL, Verilog and IC Design in general
- Deep understanding and knowledge of verification methodologies, flows and quality metrics
- Understand the architecture of the System Management Unit (SMU) IP and functional block being designed
9
Experience For Lead Asic Verification Engineer Resume
- Integrate the IPs to SOC, bring-up functionatiliy in the SOC
- Familiarity with industry standard verification methodologies like coverage, OVM/UVM and Objected Oriented Programming
- Exposer to configuration management, bug tracking tool etc
- Knowledge of scripting language, Perl TCL etc
- Able and willing to work in a team-oriented, collaborative environment
- Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc
10
Experience For MTS Asic Verification Engineer Resume
- Create self-checking and reusable test benches from scratch
- Embedded code development (C, Assembly)
- Verilog/System Verilog/SVA/VHDL, DPI, PLI, SV Constraints
- UVM Class based verification methodologies
- + Write the block level test plan
List of Typical Skills For an Asic Verification Engineer Resume
1
Skills For Senior Asic Verification Engineer Resume
- Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints
- Solid understanding of standard ASIC verification techniques, including
- Master of Science in Electrical Engineering, Computer Engineering or equivalent experience
- Experience in running hardware design language simulators utilizing constrained random techniques
- Work experience debugging RTL at the block and/or top level
- Transaction Level Modeling (TLM) experience with System C
- Demonstrated ability to conceive and develop solutions to complex engineering problems
- Good understanding in SV or UVM
2
Skills For Lead Asic Verification Engineer Resume
- Experience with Perl and C/C++ programming language
- Experience with Unix, scripting, C/C++, and/or Perl
- Five or more years of experience working as a verification engineer or related field
- Hands on experience in developing System Verilog OVM/UVM verification environment from scratch
- Excellent knowledge of C, C++ and scripting languages
3
Skills For MTS Asic Verification Engineer Resume
- Good understanding of digital electronic is an asset
- Industry experience in FPGA design, micro architecture, RTL coding for FPGA
- Hands on experience in designing DSP blocks for digital communication
- ASIC Verification Experience
- Experience with C, C++, Python, Perl
- Experience in verification strategy development and execution for large SoCs and signoff with coverage metrics
- Experience with gate level simulations of delay annotated netlists
- Experience with signoff of SoC designs with coverage metrics
4
Skills For Principal Asic Verification Engineer Resume
- Experience in ASIC/FPGA Verification
- Lab-based verification experience
- MS or BS with at least 2+ years of experience
- Strong desire to take ownership of all verification aspects of a project
- High technical competence that includes a track record of effective verification of complex digital designs
- MSEE, MSCE, or MSCS with 0-2 years of experience
5
Skills For Co-op Asic Verification Engineer Resume
- Demonstrated expertise in HDL languages, Perl, System Verilog, C, Java and other OOP techniques
- Hands on experience in DO-254 verification process
- Excellent knowledge of Verilog
- Expertise with pre-silicon hardware validation tools (UVM, System Verilog, VCS, Verdi, GDB)
- Experience with low level software/firmware and embedded systems is an asset
- Experience in ASIC/FPGA Verification
- Relevant experience in ASIC verification field
- Experience in VLSI design, verification or implementation
6
Skills For Senior. / MTS Asic Verification Engineer Resume
- Developing and maintaining complex verification environments using various methodologies, including Self-checking, reusable, automated verification
- Architecting/creating RTL test benches from scratch
- Understanding of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture
- Resolving coverage issues using coverage methodologies as well as formal methods
- Mastering object oriented programming
- Developing test plans and directed/randomized test cases from scratch
- Driving automation and innovation throughout the DV flow
- Working with simulation environments based on UVM and Google Test
- Understanding of configuration management, requirements traceability (DOORS) and related processes
7
Skills For Asic Verification Engineer Resume
- ASIC verification including writing verification plans, verification environment development, behavioral model development and test case writing
- Familiarity with reading and interpreting specifications
- RTL coding and simulation Testbench development for the verification of RTL blocks using SystemVerilog
- Work successfully with cross-functional teams, including coordinating across organizational boundaries and geographies
- Comfortable for doing lab debugging
- Work with other hardware/ software architects developing one of a kind innovative FPGA prototypes, contribute to feasibility studies & developing solutions
- B.S., or M.S. in Computer Engineering or Electrical Engineering
- Familiarity with reading and interpreting DSP specifications
- Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team
8
Skills For Senior Asic Verification Engineer Resume
- ASIC Verification using System Verilog
- Hands-on verification utilizing System Verilog/UVM
- Architect and develop reusable and scalable verification environment using System Verilog and UVM
- Execute functional verification test plans by writing tests in System Verilog, UVM, C, C++ etc
- Responsible for development, gathering and analysis of code and functional coverage metrics
9
Skills For Lead Asic Verification Engineer Resume
- Knowledge of Synplify, Xilinx Vivado (including IP integration flow), Matlab, Matlab SYSGEN, Modelsim, Synopsys’ DC Ultra, Synopsys’ PrimeTime
- Object oriented programming considered an asset
- SystemVerilog and UVM for verifying complex ASIC/FPGA
- Software driven test development using SystemVerilog and UVM
- Development of models using SystemC, C/C++, Python, Matlab
- Proficient in scripting languages: Make, Perl, Python, etc
10
Skills For MTS Asic Verification Engineer Resume
- Assist architects developing Linux/ Windows device driver, test and debug
- Design verification and design modeling
- Work in cross functional team setting
- Develop coverage models and verification environments using UVM-SystemVerilog / C++. Write, maintain and publish the verification specification
- Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time
- Long amounts of sitting
- Classroom or internship exposure to advanced verification theories using System Verilog, VMM, UVM
- Knowledge of SystemVerilog, C/C++, and scripting languages like Python or Perl
- Curious, demanding and rigorous
List of Typical Responsibilities For an Asic Verification Engineer Resume
1
Responsibilities For Senior Asic Verification Engineer Resume
- Working Practice: Effective team player with focused and independent working style
- Good understanding on synthesis, timing analysis, CDC and formal verification
- Experience in developing Testbenches for block level verification using System Verilog & UVM
- Experience in software or ASIC development, verification or implementation
- Hands on experience in SPW tool
- Hands on experience in Simulink HDL Coder
- Hands on experience in Cyclone V & Cyclone V SoC FPGAs
- Hands on experience with Questa or similar advanced simulation tools
2
Responsibilities For Lead Asic Verification Engineer Resume
- Networked communication: Developing and tracking of verification plans
- Structured evaluation: Measuring and analyzing regression results
- Testbench development for the verification of RTL blocks using SystemVerilog OVM/UVM
- Deliver high quality IP on time using RTL
- Work with front-end team and physical design team on timing closure
- Work with bring-up team on post-silicon triage
- Familiar with Verilog HDL, Shell, Perl programming
- Standard IO IPs, including SPI/SMBUS/GPIO/I2C/I2S/UART
- + Review functional and code coverage metrics – modify or add tests to meet coverage requirements
3
Responsibilities For MTS Asic Verification Engineer Resume
- + Review functional and code coverage metrics - modify or add tests to meet coverage requirements
- All aspects of block or full chip verification including infrastructure / environment development, test plan development and execution, coverage closure and reviews
- Verification flow and methodology enhancements
- Exposure to UVM methodology
- Familiarity with assertions and functional coverage
- Develop NVMe Verification test suite to test internally developed RTL IP
4
Responsibilities For Principal Asic Verification Engineer Resume
- In depth expertise in PCIe interface technologies
- In depth background in Verification development, debug, simulation, test bench creation and debug using relevant tools (Synopsys, Mentor, Cadence, or FPGA tools
- Contribute significantly to verification infrastructure development
- Development of System Verilog/UVM based protocol/traffic generators/checkers, development of test plan based on functional requirements as well as applicable standards requirements
- Relevant experience in ASIC verification field
- Knowledgeable about assertions and functional coverage
5
Responsibilities For Co-op Asic Verification Engineer Resume
- Familiarity with digital verification approaches and debug
- Write and perform the test plan in close cooperation with the logical design team
- Monitor, analyze and debug simulation errors
- Produce a maintainable and reusable code across projects
- Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages
- Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA)
- Knowledge of simulation tools and coverage database visualization tools
- The development of new infra-structure and test cases
6
Responsibilities For Senior. / MTS Asic Verification Engineer Resume
- Contribute to verification infrastructure development
- Development of System Verilog/UVM based protocol/traffic generators/checkers,
- Work on test plans based on functional requirements and applicable standards requirements
- Familiar with assertions and functional coverage
- Designs portions of computer/server architecture and algorithms based on established software engineering principles and in accordance with provided specifications and requirements
- Participates as a member of project team of other software systems engineers including internal and outsourced development partners to develop reliable high quality solutions for low to moderately- complex products
- Contribute to hardware engineering requirements capture, analysis and creation in area of domain expertise
7
Responsibilities For Asic Verification Engineer Resume
- Contribute to the engineering estimates for moderate to large scope electrical design problems
- Participate in cross-functional team efforts in integration, pre- qualification and qualification for products and sub-systems of moderate to high complexity
- Review metrics and hardware defects trends, identify systemic root causes and process improvements
- Be responsile for System Management IP design. Focus on one or multiple areas including (but not limited to): chip reset and bootcode, security, power management (power-gating, voltage island etc), Network on Chip (NOC), Clocking, platfrom IOs (GPIO, SPI, I2C, etc), data compression engine and DMA, OTP/FUSE, thermal solution, etc
- Work with verification team to create concrete testplan, and to achieve good coverage
8
Responsibilities For Senior Asic Verification Engineer Resume
- Experience on design from a system point of view
- Micro-processor (e.g. ARM) architecture and peripheral
- Popular on-chip bus (AMBA/AXI) or NOC
- Low power design and verification methodology
- Think holistically: Coverage-/metric-driven verification
- Observe, and think ahead: Digital centric and mixed-signal centric simulation
- Reliable implementation: Integration of verification IP
9
Responsibilities For Lead Asic Verification Engineer Resume
- Conscientious coordination: Continuous improvement of verification methods, tools, flows and processes together with EDA partners
- Personality: High level of enthusiasm, creativity and willingness to work in international and interdisciplinary teams
- Knowledge: Deep knowledge of different ASIC verification methodologies (coverage-driven verification, formal verification, directed testing) as well as analog modeling styles and abstractions (real-numbered modeling, Matlab, SystemC) and their usage in the verification process desired
- Languages: German B2 and English C1
- Assist in the creation of verification test plans for block level or full chip RTL verification
- Execution of the block or system level test plans
- Review code coverage and functional coverage reports and improve/add test sequences as required
- Participate in peer code reviews, verification test plan reviews etc
- Exposure to industry standard verification tools for simulation and debug
10
Responsibilities For MTS Asic Verification Engineer Resume
- Write the block level verification plan
- Create directed and random block level verification tests and functional cover points
- Provides technical expertise to a project team of Electronic and VLSI engineers along with development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing
- Collaborates and communicates with management and internal partners regarding design status, project progress, and issue resolution
- Represents the team for all phases of larger and more complex VLSI development projects
- Participates as an independent member of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products
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