DFT Engineer Resume Sample
Bria Kozey
2132 Prohaska Roads,
San Francisco,
CA
+1 (555) 188 3969
Work Experience
Senior DFT Engineer
09/2016
-
PRESENT
Detroit, MI
- BS in EE & CS, with 0-2years’ experience
- BS in EE & CS, with 5+ years’ experience
- Fluent in STA & SDC’s
- MS or PHD in Electrical or Computer Engineering- Eperience in RTL environments and/or silicon design/validation.- Experience with RTL environments such as Verilog- Knowledge of the DFT concepts
- DFT Solutions which need to be integrated and verified: Test control (test modes), Memory BIST, Scan (On-Chip Compression/At-speed Scan/Test-clocking), Boundary Scan, Analog Test Subsystem, Test Pin-Muxing, Logic BIST
- Be responsible for the in-time delivery of DFT production pattern according to our quality metrics
- Working experience in the EE industry
DFT Engineer
11/2009
-
05/2016
Detroit, MI
- Understanding of ASIC design flow and DFT concept
- Multi-task, set priorities, and works in a strong team environment
- Help the team with architect in delivering efficient workflows and tools to help productize these features on industry's leading processors for deep learning, gaming, HPC and super computing
- Be responsible for crafting key DFT logic modules
- Collaborate closely with other teams like chip architecture, ASIC design, verification, CAD, VLSI and Operations teams productize new methodologies
- Perform ATPG stuck-at and transition fault pattern generation & coverage analysis
- Perform JTAG, Bscan, DC parametric and Mbist test pattern generation and simulations
MTS DFT Engineer
04/2003
-
09/2009
New York, NY
- Work with Customer Engineers to suggest implementation to improve test coverage
- Work with Test Engineers to debug test pattern failures
- Work with circuit designers to drive all testability issues to closure
- Define DFT architecture for new device families which includes testability for core logics, memories, PLL and DLL
- Develop DFT flow for macro & fullchip level to support DC scan, AC scan, scan compression, BIST and etc
- Experience in DFT (including Silicon debug) is desirable
- Experience in DFT / design field
- Strong logic Design and verification back ground
- MSEE + 3 years of experience in depth technical background for DFT
Education
Indiana Wesleyan University - Kokomo Campus
1998 - 2002
Engineer's Degree in Computer
Professional Skills
- Strong communation skills and previous experience leading chip DFT development and working in cross functional manner across development teams
- Strong programming skill in Verilog and hands-on experience working with test bench creation and debugging
- Excellent programming skills with scripting languages such as Perl/TCL/Python
- Demonstrate outstanding problem solving and analytic skills
- Excellent problem solving, debug , root cause analysis and communication skills
- Strong knowledge of Computer Systems and Skills
- Experience with 5+ years of silicon design and validation Experience
How to write DFT Engineer Resume
DFT Engineer role is responsible for scripting, languages, programming, digital, design, analysis, integration, architecture, planning, manufacturing.
To write great resume for dft engineer job, your resume must include:
- Your contact information
- Work experience
- Education
- Skill listing
Contact Information For DFT Engineer Resume
The section contact information is important in your dft engineer resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:
- First and last name
- Telephone number
Work Experience in Your DFT Engineer Resume
The section work experience is an essential part of your dft engineer resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous dft engineer responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular dft engineer position you're applying to.
The work experience section should be the detailed summary of your latest 3 or 4 positions.
Representative DFT Engineer resume experience can include:
- Excellent debug skills required
- Strong interpersonal and communication skills#LI-ZL1
- Good communication skills, works well in a group environment that spans across continents
- Perl, shell scripting skills as well as Linux OS environment are assumed
- Experience in RTL environments and/or silicon design/validation
- Good communication skill and has to be able to works well in a group environment that spans across continents
Education on a DFT Engineer Resume
Make sure to make education a priority on your dft engineer resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your dft engineer experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.
Additional details to include:
- School you graduated from
- Major/ minor
- Year of graduation
- Location of school
These are the four additional pieces of information you should mention when listing your education on your resume.
Professional Skills in DFT Engineer Resume
When listing skills on your dft engineer resume, remember always to be honest about your level of ability. Include the Skills section after experience.
Present the most important skills in your resume, there's a list of typical dft engineer skills:
- Good team player with good interpersonal, planning and communication skills
- Good communications and reporting skills
- Good communication skills, works well in a group environment that spans across continent
- Hardware Engineering experience or related work experience
- Good language skill in English, Pass CET-6
- Validating & Debugging Test vectors on ATE during the silicon bring up phase
List of Typical Experience For a DFT Engineer Resume
1
Experience For Senior DFT Engineer Resume
- Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Verifying test pattern functionality and fault coverage through pre-silicon
- Creating functional test patterns with built-in diagnosis capability to be executed in the ATE environment
- Debugging test pattern issues on bench/ATE to understand failure mechanism and improve yield
- Working closely with IC Design, NPI, Product and Test Teams to ensure timely delivery of robust test patterns
- Architecting automation strategies that align with third party DFT tools and create further efficiencies
- Working with Product Engineer to address Yield, Design & Quality issues during New Product Introduction phase and also to address any post production issues
- Balancing Test Time with quality to meet product requirements
2
Experience For Senior Principal DFT Engineer Resume
- Defining DFT requirements for next generation SERDES to improve test coverage or time
- Developing high coverage functional BIST patterns, built in FPGA fabric, to test the embedded SERDES
- Working closely with STA and design engineers design closure
- Assisting with silicon failure analysis, diagnostics & yield improvement efforts
- Debugging customer returned parts on the ATE
- Innovating newer DFT solutions to solve testability problems in 7nm & beyond
- Automating DFT & Test Vector Generation flows
- Working closely with STA and DI Engineers design closure for test
3
Experience For SOC DFT Engineer Resume
- Working closely with I/P DFT engineers & other stakeholders
- ATPG - Stuck-at, Transition, Path Delay, bridging and dynamic bridging, small delay defect models handling
- Proficiency with programming and scripting languages such as Perl/TCL
- DFT Verification (including post place-and-route timing simulations)
- Work with Product Engineering team to bring up scan & mbist patterns on ATE
- Proficiency with programming and scripting languages such as Perl/TCL/Python
- Work with RTL, custom digital/analog, verification, physical implementation, and timing teams during this DFT implementation
4
Experience For MTS DFT Engineer Resume
- Education: BSc. in Electrical Engineering or Computer engineering or Student
- Knowledge in CMOS or FPGA design/verification, and EDA tools such as Cadence/Synopsys (simulation, fault grading, schematic and waveform viewing)
- Some knowledge of Synthesis, IC routing and static timing tools
- Work closely with Place and Route team to achieve timing closure in all test modes
- Knowledge of Logic design and timing
- Signoff Full chip timing
- Drive successful bring-up of test patterns and features post tape-out
5
Experience For Cpu-dft Engineer Resume
- Lead the root cause of complex process/design issues using our state of the art onsite EFA lab
- Test patterns (including silicon debug)
- Tessent, DFTC, TCL/PERL, IEEE 1149 and 1687, Primetime, SpyGlass, Verilog simulation including SDF, Advantest ATE
- Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation, and at-speed testing
- Fault modeling (Stuck-at, Transition, Path Delay, Gate Exhaustive, IDDQ and other advanced DTF models
6
Experience For Mixed Signal DFT Engineer Resume
- Fluency in writing synthesizable RTL
- STA timing constraints
- Transition & Path delay testing
- Expertise in industry standards and practices in DFT, including JTAG/BSCAN, at-speed Scan-ATPG, MBIST and trade-offs between test quality and test time
- Expertise in debugging ATPG patterns, MBIST setup/patterns, and JTAG/ IEEE1500
7
Experience For DFT Engineer Resume
- At speed testing of 3GHz+ CPU clusters,
- Scan testing methods
- At-speed testing of high-speed I/O
- Fault grading of functional vectors
- Proper handling of analog circuits (PLLs, I/Os, etc)
8
Experience For Senior DFT Engineer Resume
- Some background in IC RTL design and using Verilog/SystemVerilog
- Some knowledge of Synthesis and static timing process
- Personal: Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
- Knowledge of the DFT concepts
- Scan Insertion, TestKompression, ATPG, Memory BIST and JTAG for mixed signal SOC
- Configuration, programming and diagnosis, of the CRAM, is accomplished through C code running in an embedded Microcontroller, therefore validation and maintenance of this code is part of this role’s responsibility
9
Experience For Senior Principal DFT Engineer Resume
- Experience in verification and/or design of digital or mixed signal ICs with special interest in SRAM experience
- BS/MS EE with relevant logic design/test background. 3-5 years’ work experience as a DFT engineer
- MS in EE or Computer Science
- Developing high coverage functional BIST patterns, built in FPGA fabric, to test the embedded SERDES and high-speed/Multi-gigabit serial protocol controllers (SATA, PCI Express, Interlaken, Ethernet, USB, etc.)
- Fault Grade and analyse functional test patterns to ensure highest quality
- JTAG Boundary Scan Design & implementation
10
Experience For SOC DFT Engineer Resume
- Travel domestically and internationally as needed (~15%)
- DFT implementation (Scan, Compression & MBIST) from RTL to Post-Production for complex multi-million gate SoC
- Develop/Generate high-quality scan and mbist patterns
- Knowledge of DFT fundamentals
- Knowledge of Verilog, Perl & Python
List of Typical Skills For a DFT Engineer Resume
1
Skills For Senior DFT Engineer Resume
- Experience with board/bench debug features and capabilities strongly desired
- Working closely with IC Design during pre-silicon verification (chip level verification) and post silicon validation
- Developing high coverage, cost-effective methodology to test the FPGA clocking resources such as the adaptive deskew circuit and Phase-Locked Loop
- Understanding of chip debug features and capabilities strongly desired
- Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, ? etc)
- Experience in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
- Test vector planning for bring-up and production, and hand-on ATE bring-up experience
- Experience and knowledge of Synthesis, IC routing and static timing tools
2
Skills For Senior Principal DFT Engineer Resume
- Experience in RTL coding, shell scripting
- MS in Electrical / Computer Engineering or BS in Electrical/Computer Engineering with 3yrs of experience in DFT implementation
- Strong understanding of DFT clocking and architecture to drive overall implementation
- Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
- Low-power testing and leakage mode validation
- Strong understanding of core based test methodology, and scan isolation
- Experience in Logic Design, VDHL, Verilog RTL verification, and static timing analysis
- Experience in many of the following areas is required
3
Skills For SOC DFT Engineer Resume
- Relevant experience working on design and functional verification
- Experience with FPGA design flow and timing closure
- Good understanding of scan test, functional test, JTAG, and other test methodologies
- Strong background in industry standard scan test (including scan compression) and memory BIST/BISR tools
- Strong background in IC RTL design and using Verilog/SystemVerilog
- Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements
- Experience in handling analog DfT simulations
- Experience in coding in C for embedded processors is highly desirable
- Experience in memory BIST knowledge to support in verifying the core level memory BIST solution
4
Skills For MTS DFT Engineer Resume
- Experience are required in the following areas
- Hands on working experience on ASIC DFT design and verification, familiar with entire ASIC design flow
- Experience in Verilog coding, testbench generation & simulation
- Experience working on ATE and post-silicon qualification
- Experience in Verilog/VHDL including behavior model construction and verification is
- BSEE or equivalent with 10+ years of experience in design for test
- BSEE or equivalent with 7+ years of experience in DFT
- BSEE with 2+ years of experience in DFT
5
Skills For Cpu-dft Engineer Resume
- BSEE or equivalent with 3+ years of experience in DFT
- Well communication and Inter-person skill
- Good knowledge in Verilog, VHDL and script language
- Handle the test patterns validation flow on RTL & gate levels
- Support test patterns validation on silicon with Test/Product Engineers
- Stuck-at and at-speed vector generation, simulation, and validation
- Professional engineering experience
- Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test, or Mentor Fastscan ATPG tools
- Experience in a semiconductor company as a DFT engineer
6
Skills For Mixed Signal DFT Engineer Resume
- Experience with High Speed Giga Bit Transceivers (GT) is highly desirable
- Hands-on experience with scan test, logic and memory BIST/BISR, functional test, JTAG, and other test methodologies
- Experience and knowledge of functional verification, especially of DFT features
- Experience and knowledge of modern JTAG standards and implementation
- Experience and knowledge of high-volume test equipment (ATE) and system-level test (SLT)
7
Skills For DFT Engineer Resume
- Work experience as a DFT engineer
- Experience with industry standard DFT tools such as Synopsys or Mentor
- In-depth direct experience in DFT methods and implementation required
- BS/MS EE with relevant logic design/test background. 2-4 years’ work experience as a DFT engineer
- Experience in scan architecture, scan insertion and ATPG
- Experienced in Mentor or Synopsys DFT tools
- Strong background in industry standard scan test (including scan compression, core wrapping, etc.)
- Hands-on experience with scan test, functional test, JTAG, and other test methodologies
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
8
Skills For Senior DFT Engineer Resume
- Customized Memory BIST insertion and verification experience (SRAM, SRF, multi-ported memories, TCAM)
- Solid knowledge in analog and digital circuit design, and device physics fundamentals
- Logic BIST design and debug experience
- Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
- Total Industry (SoC) Experience
- Proven track record in SoC DFT methodology development
- DfT experience in the semiconductors industry
9
Skills For Senior Principal DFT Engineer Resume
- Experience in Industrial ATPG tools, Logic simulation tools
- Defining and executing DFT-related tool flows, spanning insertion, ATPG, as well as DFT requirements in front-to-back SoC implementation flows
- Understanding DFT architecture and feature requirements, meeting DPPM goals, and defining appropriate DFT specifications
- Generating, Verifying & Debugging Test vectors before tape release
- Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
- Creating and implementing test plans for core Xilinx product functionality to be
- Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques
10
Skills For SOC DFT Engineer Resume
- Achieving high coverage via SAF, TDF, as well as knowledge of other techniques such as Small Delay Defects, Path testing, LOC/LOS, etc
- Creating test plans and working with IC Design to define and implement desirable DFT features
- Verifying test pattern functionality and fault coverage through pre-silicon simulation and fault grading
- Building or contributing to a scalable pattern development methodology to efficiently test highly configurable embedded SERDES
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO BSCAN, SerDes and other IP DFT integration
List of Typical Responsibilities For a DFT Engineer Resume
1
Responsibilities For Senior DFT Engineer Resume
- Groups blocks to generate tiles for synthesis
- Run synthesis regression to monitor tile/block status
- Synthesis and deliver netlist that meeting timing, area and power requirement. Resolve formality. Lint and CDC issue. Help PD on the floor planning and close timing
- Scan insertion, Memory Bist insertion and verification
- Set-up, run, and debug block-level, SOC-level as well as full-chip ATPG runs
- Understand and then improve upon our DFT architecture for future products
- Finally, add to the in-house expertise of DFT to consult with, educate and train design members from other teams on our DFT requirements as well as on how to prepare future designs based on Cavium DFT architecture
- Understand and then implement the Cavium DFT architecture
- BSEE / MSEE is required
2
Responsibilities For Senior Principal DFT Engineer Resume
- Fault Grade and analyse functional BIST patterns to ensure highest quality
- Lead team of 4-5 DFT engineers in project and test chip DFT implementation
- Scan Insertion and scan compression background (Mentor Tessent and LogicVision)
- Well-versed in ATPG vector generation, simulation, debug
- The ability to work in a multi-disciplined, cross-department environment
- Perform ATPG stuck-at and transition fault pattern generation & coverage analysis and
- Work with circuit designers to solve testability issues
3
Responsibilities For SOC DFT Engineer Resume
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
- Well-versed in ATPG vector generation, simulation, debug. (TetraMax, Fastscan)
- Exepriance
- Experience leading large DFT/ATPG teams and defining/bring-up of DFT architecture, including hierarchical core/chip based flows and pattern retargeting - Experience with large device test on ATE and with architecting DFT strategies in support of multi-core and parallel testing
- Design for Test/Design for Debug (DTF/DFD)
- Synopsys DFTC Scan Insertion
- BSEE and/or MSEESearch Jobs US
- Knowledgeable in high speed serial protocols (SATA, PCI Express, Interlaken, Ethernet, USB, etc.)
4
Responsibilities For MTS DFT Engineer Resume
- In SoC Design
- In DFT Methodology/Implementation
- Memory BIST Algorithm development and implementation
- At-speed, Diagnostic for Failure Analysis
- JTAG Boundry Scan Design & implementation
- IC Parametric test methods and implementation
- Low pin-count test methods
5
Responsibilities For Cpu-dft Engineer Resume
- IP test methods & implementation
- PLL, DLL, A/D, D/A, Transceivers: LVDS, PCI-e, XAUI, USB, SPI
- Travel domestically and internationally as needed (~15-20%)
- , of experince in DFT
- Digital ASIC front end Design and verification
- Familiarity with modern mobile SOC architectures
- Low power design practices would be an advantage
- We collaborate with multi-functional teams like architecture, front-end design, verification, timing, physical design, and CAD team on defining DFT solution, implementing IP modules, making chip integration for the IP design and running unit and full chip verification
6
Responsibilities For Mixed Signal DFT Engineer Resume
- Implement, verify and enhance test vehicle DFT and DFx logic. This includes being involved in all details of the ATE test strategy
- Have used Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor digital and/or analog developing
- High-speed SerDes I/O testing methodology
- Your job responsibilities also include silicon bringup of various DFX features
- B.Tech or M.Tech in Electronics, Electrical, VLSI
- MBIST (Memory Build In Self-Test)
- LogicBist (Logic Build In Self-Test)
- Creation and verification of test mode controllers,
7
Responsibilities For DFT Engineer Resume
- BSCAN, Iee1500 Wrapper insertion
- Fault simulation, coverage analysis, Silicon debug etc
- Stuck-at and at-speed scan insertion
- IEEE 1149.1, IEEE1149.6, IEEE 1500, and IEEE 1687 test feature standards
- Stuck-at and at-speed fault analysis
- IP integration into larger SoC environments
- Improve test structures and test patterns for better defect isolation and characterization
- Implement and improve a variety of automation scripts used to implement test vehicles and isolate failures
- Interact with internal and external cross-functional groups to determine and fulfill design automation needs
8
Responsibilities For Senior DFT Engineer Resume
- Work as part of a team to design and implement in-silicon monitor structures
- Create innovative DFT IPs - RTL design (Verilog) – Verification – release and deployment
- Use of IEEE standards (1149.x, 1687…): register configuration and insertion at RTL
- Memory BIST configuration and insertion
- Develop functional test pattern to maximize the test quality
9
Responsibilities For Senior Principal DFT Engineer Resume
- ATPG generation and verification
- Automate as much as possible the different DFT tasks
- Execution of test patterns handoff to Test/Product Engineers
- Some knowledge of functional verification, especially of DFT features
- Goof knowledge of high-volume test equipment (ATE) and system-level test (SLT)
- Have knowledge about EDA tool as well as VLSI design flow
10
Responsibilities For SOC DFT Engineer Resume
- JTAG and boundary-scan test methodology
- Structural Test design requirements
- Work well with overseas partners
- On-product clock generation
- Volume silicon production
- Logic simulation tools
- Chip failure analysis
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