Staff Verification Engineer Resume Sample
Rey Weber
186 Rowe Extensions,
Phoenix,
AZ
+1 (555) 571 6344
Work Experience
Senior Staff Verification Engineer
03/2017
-
PRESENT
Boston, MA
- BSEE or MSEE with 10 years of professional IC design experience with strong emphasis on mixed-signal design/verification
- Strong ability to build verification environments using the verification subset of high level languages like System Verilog (OVM,)
- Proficiency in scripting language like Perl, Tcl/Tk, Shell
- Experience with simulators like ncVerilog (Incisive), VCS, Cadence ADE-AMS and debug tools like DVE, Verdi/Debussy
- Good understanding of latest formal verification techniques, assertions, OOP and experience with cosims, gate verilog, and RTL synthesis
- Experience with working on mixed-signal design projects that have a high level of integration between the analog and digital domain
- Good written and oral communication skills. Ability to clearly document plans
Staff Verification Engineer
06/2012
-
10/2016
Philadelphia, PA
- Planning and estimation of the work
- Verification closure to ensure bug-free designs
- Excellent communication skill verbally and in writing
- Experience of functional units in Microprocessor-based SOC products
- Strong programming skills using C++ and Verilog
- Experience with writing a detailed test plan, and building a sophisticated directed random verification environment
- Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses and memory interfaces
- Experience in working with EDA verification tools (e,g; waveform viewers, coverage tools etc.)
Staff Product Verification Engineer
06/2009
-
04/2012
Houston, TX
- Coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc
- Development and implementation of verification testbenches, testbench components and bus-functional models in SystemVerilog using standardized verification methodologies such as UVM
- Definition, documenting and execution of verification test plans to verify complex block or sub-system level designs (250K to 5M+ gates) leveraging coverage metrics and constrained random-driven verification techniques
- Collaboration in partnership with design and software teams to plan verification activities, including release schedule of testbench environments enabling agile development
- Participation in the execution of validation phase feature test plan focused on low level and system level testing with actual prototypes in validation lab
- Contribution to software development kit (SDK) deliverable by defining and reusing C-drivers, or programming sequences, outlined in the verification test plan
- Verification work or research experience is an asset
- Strong background, or work experience, in software with object oriented programming is a requirement for ASIC verification
- Excellent analytical and debugging skills and the ability to proactively solve issues is required
Education
Fairleigh Dickinson University - Metropolitan Campus
2005 - 2009
Engineer's Degree in Electrical Engineering
Professional Skills
- Strong communication skills and ability to work well as part of a team as well as experience working and communicating with remote design centres
- Excellent system view capabilities and debug skills
- Excellent English language skills, both written and spoken, are needed
- Strong communications skills and capability
- Fluent English and excellent communication skills (both written and verbal)
- Engineering experience in CPU verification with Technical leadership experience
- Knowledge and experience with Perl/Tcl and Unix/Linux Makefile scripting strongly desired
How to write Staff Verification Engineer Resume
Staff Verification Engineer role is responsible for communications, scripting, english, architecture, integration, database, reporting, design, research, assembly.
To write great resume for staff verification engineer job, your resume must include:
- Your contact information
- Work experience
- Education
- Skill listing
Contact Information For Staff Verification Engineer Resume
The section contact information is important in your staff verification engineer resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:
- First and last name
- Telephone number
Work Experience in Your Staff Verification Engineer Resume
The section work experience is an essential part of your staff verification engineer resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous staff verification engineer responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular staff verification engineer position you're applying to.
The work experience section should be the detailed summary of your latest 3 or 4 positions.
Representative Staff Verification Engineer resume experience can include:
- Strong hands on experience in System Verilog and UVM
- Strong communications skill and capability
- Very good hands on experience in developing Module and SoC based Chip level Test bench
- Experienced with verification EDA tools. Be good at tool usage exploration
- Prior experience in verification/design of mixed signal SOC components
- Strong written and verbal communications skill required for rapid bug closure
Education on a Staff Verification Engineer Resume
Make sure to make education a priority on your staff verification engineer resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your staff verification engineer experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.
Additional details to include:
- School you graduated from
- Major/ minor
- Year of graduation
- Location of school
These are the four additional pieces of information you should mention when listing your education on your resume.
Professional Skills in Staff Verification Engineer Resume
When listing skills on your staff verification engineer resume, remember always to be honest about your level of ability. Include the Skills section after experience.
Present the most important skills in your resume, there's a list of typical staff verification engineer skills:
- Experience developing re-usable and scalable code whilst having good knowledge of UVM
- Engineering experience in CPU verification or CPU based SoC validation
- Proven track record of Technical Leadership working with a team of highly skilled engineers
- Strong working knowledge in SystemVerilog, C and UVM, experienced in DPI integration
- Experience in System Verilog is strongly desired
- Experience with emulation flows. Experience with Functional Safety aspects of Design / Verification, knowledge of ISO 26262
List of Typical Experience For a Staff Verification Engineer Resume
1
Experience For Staff Design Verification Engineer Resume
- Experience in HW Verification developing, methodologies and implementation
- Experience and understanding of Random Verification concepts, methodologies and Environments
- Experience and understanding of Coverage driven verification techniques
- Verifying various features using targeted/random/corner-case/coverage tests
- Working on IP as well as SoC level verification and using advance verification methodologies[UVM,VMM,OVM]
- Coming up with design automation techniques for increasing execution efficiency
2
Experience For Staff Product Verification Engineer Resume
- Planning and writing Verification plans and test-plans
- Understanding of the fundamentals of computer architecture, with an emphasis on memory, pipelining or dpu
- Developing UVM testbenches for logic verification
- Being able to work independently with limited or no supervision
- Working with Architecture and Design teams to prepare and develop robust verification plan
- Planning and coordination of resources and team members to meet Design Verification goals on time and within budget
- Understanding of constrained random stimulus,
3
Experience For Staff CPU Verification Engineer Resume
- Checking methodologies and behavioural functional models
- Programming in C/C++, Perl, Python, Ruby, Java, TCL, etc
- B.Sc. in Electrical Engineering, Computer Engineering, Computer Science/Software Engineering
- In-depth understanding of memory protection, memory translation, vector processing in CPUs, exception and interrupt handling
- Develop randomized and targeting test stimulus ensuring coverage goals for the design
4
Experience For Senior Staff Verification Engineer Resume
- Use scripting knowledge to build automation layer/apis for the software being developed
- Execution of CPU DV with focus on improvement of IP quality; stress testing and bug hunting
- Education/Field Requirements: Electrical Engineering, Computer Engineering or related equivalent
- Knowledge of either of the following Hardware Verification languages is a requirement: SystemVerilog, Specman E or SystemC
- Work in a Linux shell environment and Linux scripting (CSH/TCL/Perl) is required
5
Experience For Staff Design & Verification Engineer Resume
- Test bench components and exposure to layered VIP component development using System Verilog and UVM flows
- Execution of the test plan and report coverage including functional, code and other metrics
- Exposure to scripting languages e.g. Perl, TCL for simulation automation and regression
- Detailed debug and root-cause analysis of full-chip simulations failures, including RTL and digital circuits
- Knowledge of scripting, such as Perl, Cshell, Kshell, or Python
6
Experience For Staff Verification Design Engineer Resume
- Technical mentoring for junior team members along with execution responsibilities
- Drive leading edge verification methodology
- Verify blocks at SoC level using firmware (C code) and other standard verification languages/constructs like SV, assertions etc
- Participate in entire SoC verification flow from initial testbench setup, then achieving verification closure and then post Si bringup support
- Lead and plan verification of complex digital design blocks by fully understanding the architecture and design specification
- Own development/testing of an ARM processor Instruction Set Simulator
- Work closely with architects/verification engineers for testing/debug purposes
7
Experience For Staff Formal Verification Engineer Resume
- Develop test plans and test cases according to product definition documents
- Work closely with global teams for problem solving
- SoC system performance profiling, system stress test
- Develop verification infrastructure and reporting tools
- Ownership of a specific area of projects ranging from unit-level testbench development through to the overall verification methodology for a project
8
Experience For Staff System Verification & Validation Engineer Resume
- CPU DV requirement collection from CPU design teams and ensure they accurately transferred into a meaningful engineering project
- Define test plan and Coverage and review of them with the leads and design engineer
- Development of the test bench suitable to cover all the aspects of the test plan
- MSc or equivalent in EE / EC
- Familiar with constraint random based verification, functional coverage, code coverage and assertions
- Testplan documentation and code reviews
9
Experience For Staff Digital Design & Verification Engineer Resume
- Regression management and code/functional coverage analysis
- Continual enhancements to testbench architecture and verification methodology
- Knowledge of FLASH design, FLASH controller and storage devices is desirable
- Develop verification environment and deploy innovative solutions to have efficient and robust pre-silicon verification
- Work with cross functional and multi geographical teams
10
Experience For Staff Asic / Fpga Verification Engineer Resume
- Work closely with program/project managers to scope and assign tasks to team members
- Responsible for a comprehensive verification plan and drive the implementation of verification test cases from applications and other sources
- Work with designer to get a full deep insight on the design and develop stressful test plan for SoC and IPs
- Build test bench and create testcase to ensure test coverage
- Run simulation in both RTL and netlist level, debug and fix issues, create test reports
- Run regression test for each design (RTL/netlist) update
- Develop verification IP which can be reused at different level verification
- Co-work with FPGA engineer to prepare test vector, support test and debug
List of Typical Skills For a Staff Verification Engineer Resume
1
Skills For Staff Design Verification Engineer Resume
- Intel or Industry experience in CPU IP validation
- Experience with Design Verification/validation best practices such as Test Plan development, Testbench development and execution thereof
- Experience and strong aptitude for People Management
- Education & Soft skills
- Working on IP as well as SoC level verification and using advance emulation platform for effective and efficient pre-silicon verification
- Experience of mentoring Developing and coaching
- Experience in specifying and developing the verification infrastructure for verifying CPU/DSP/Vector-datapath designs
- Good digital signal processing background and be familiar with video processing algorithm, be familiar with MATLAB
- Experience in talent management including recruitment, team building as well as performance management for engineers
2
Skills For Staff Product Verification Engineer Resume
- Good understanding of resource management and appreciation for operational aspects such as budgeting, cost management
- Extensive Experience of Designing and implementing verification environments for complex RTL designs
- Has good understanding of event-driven simulator based modeling techniques
- Experience leading technical activities
- Detailed practical experience of working on microprocessor designs
- Min 4 years experience in code coverage tools and debugging tools
3
Skills For Staff CPU Verification Engineer Resume
- Experience with mixed-signal SOC designs with industry-leading embedded MCUs
- Good to have Programming Knowledge; i.e, C, C++
- Strong analytical problem solving, and attention to detail
- Experienced in building test benches, checkers, test vectors, assertions, coverage analysis
- Experienced with verification environment and flow build up, using UVM and Metric-Driven verification methodology
- Experience with formal verification with exposure of FPGA and/or emulation flows
- Hold strong opinions lightly
- Experience in HW Verification developing, methodologies and implementation
4
Skills For Senior Staff Verification Engineer Resume
- Strong Programming in Perl, Python
- Experience in System Verilog and System Verilog UVM
- Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, Cadence IES or Mentor Questa is required
- Industry experience in verification
- Experience in the verification of complex digital systems
- Proven track record for successful design of IC products in the past
- Good background in C, Verilog, SystemVerilog and verification methodology
5
Skills For Staff Design & Verification Engineer Resume
- A strong knowledge of digital design to include one or more from CPU, GPU and cache concepts, memory, I/O, etc
- Experience and Knowledge of AXI4/AxiLite/AHB is needed
- 5+ member team with strong technical contribution
- Ability/experience to define DV methodology, process and infrastructure for ‘start from scratch’ verification projects
- Validation environment development in System C, System Verilog, VCS, Specman, UVM/OVM, or similar
6
Skills For Staff Verification Design Engineer Resume
- Experience in an IP/SOC product development environment
- Experience of ARM based System Designs, Knowledge of CPU and hierarchical memory system
- Video, GPU, Display or ISP verification experience
- Experience with RTL and simulators and familiarity with ARM architectures and instruction sets
- SoC verification experience
- Experience as a Staff Engineer, Application Engineer, or related occupation
- 3) Strong academic background required
- 4) Good grasp on fundamentals like Verilog, System Verilog, assertions etc required
7
Skills For Staff Formal Verification Engineer Resume
- Experience in complex SoC verification
- Experience with System Verilog preferably UVM
- Experience in design verification in Verilog or systemVerilog environment
- Have experience creating Engineering Requirements, Technical Overviews, Verification Plans
- Significant experience in module level / SoC verification using standard UVM and System Verilog methodologies
- Experience in building BFM and C++ models of various SoC blocks
- Experience in developing automation flow and scripts with Perl, Makefile, Tcl and UNIX shell
- Have extensive experience in SOC development in areas such as IoT, automotive or mobile applications
- Have the ability to lead and mentor lesser experienced engineers
8
Skills For Staff System Verification & Validation Engineer Resume
- Strong academic qualifications and Bachelors/Masters from an institution of repute
- Experience in relevant fields
- Verification work or research experience is an asset
- Good to have knowledge of Ref Model Development
- Good to have knowledge of Gate Level Verification
9
Skills For Staff Digital Design & Verification Engineer Resume
- 10+ total of which 4+ years of experience in the verification of CPU/Video/DSP/vector processors, SIMD, etc
- Experienced in SoC verification and debug, be familiar with ARM processor and AXI/AHB protocol
- Work experience
- Hands-on experience in digital verification of SoC or mixed-signal chips
- Experience in verification lead
- Experienced with constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
10
Skills For Staff Asic / Fpga Verification Engineer Resume
- Developing verification components, preparing and executing test plan for complex Video, Imaging and/or Audio IPs
- Understanding of the fundamentals of computer architecture with emphasis on pipelining, exception handling, memory systems
- Developing methodology and deploying within the group and having full ownership of verification closure
- Developing verification components, preparing and executing test plan for SOC, interface IP, memory sub-system and co/processor
- Designing testbench building blocks using native system Verilog/VMM/UVM methodology
- Understanding design microarchitecture and writing testplans, developing tests and coverage metrics
- Understanding of machine learning, neural networks, automotive or computer vision applications
- Understanding of assembly language programming
List of Typical Responsibilities For a Staff Verification Engineer Resume
1
Responsibilities For Staff Design Verification Engineer Resume
- Good knowledge in the SoC architecture, AXI/AHB protocol. Experienced in full chip verification plan, execution and sign-off
- Experience with any one HDL simulator is good but need to be savvy with simulation/methodology/emulation and verification tools
- Relevant experience in SoC verification i.e. developing verification components, preparing and executing test plan
- Good understanding of SoC buses i.e. AHB, AXI or similar buses
- Excellent debugging and analytical abilities
- Experience in using various new EDA tools
2
Responsibilities For Staff Product Verification Engineer Resume
- Good knowledge in SystemVerilog, C/C++ and UVM
- Experienced in system performance test
- 10 total of which 4 years of experience in the verification of CPU/Video/DSP/vector processors, SIMD, etc
- Verification experience in IP/Silicon/Subsystem Verification
- Logic Design experience – an advantage
3
Responsibilities For Staff CPU Verification Engineer Resume
- Experience in System Verilog
- Knowledge in writing assertions, OVM/UVM, etc
- In-Depth Understanding of end-to-end verification processes, from test plan creation through to verification closure
- Power aware and Clock Domain Crossing verification
- Verification closure using coverage metrics
- Verification Automation using scripts like Perl,shell,tcl/tk
- Expertise in following CAD Tools
4
Responsibilities For Senior Staff Verification Engineer Resume
- Development of SystemVerilog based verification environment using OVM, UVM, or VMM verification methodologies
- Detailed understanding of end-to-end verification processes, from test plan creation through to verification closure
- MS in electrical engineering or equivalent field
- Proficiency in Perl, Python and/or other scripting language
- Verification team leading – an advantage
5
Responsibilities For Staff Design & Verification Engineer Resume
- Recognise the power in saying don't know
- Dedicated and a focused approach to problem analysis and solving
- Develop verification test plans from architectural and design specifications
- Develop environments for execution of block and chip level verification test plans
- Assist in silicon debug and customer issue reproduction in simulation
6
Responsibilities For Staff Verification Design Engineer Resume
- Interact with architects and design engineers to create a comprehensive verification testplan
- Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
- Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
- Identify and write coverage measures for stimulus quality measurements
- Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
7
Responsibilities For Staff Formal Verification Engineer Resume
- Understand micro-architecture/implementation details of specific proprietary areas to implement them in the software model
- Support CPU design/verification teams for simulator enhancements/issues
- Build a UVM based bench for the functional verification of mixed-signal chips
- Handle functional and code coverage development, analysis and closure
- Lead verification on both block and system level in major projects
- Work on initiatives to improve verification methodology, in terms of quality and productivity
8
Responsibilities For Staff System Verification & Validation Engineer Resume
- Proficient with verification language (Verilog, System Verilog, Assertion, C++, etc.)
- Verification (Formal, SystemVerilog, UVM, Power Aware)
- Project Management of verifcation teams
- B.E/B. Tech/M. Tech (ECE or Computer Science)
- Relevant experience in SoC verification i.e. developing verification components, preparing and executing test plan for complex Video, Imaging and/or Audio IPs
- Good understanding and experience in HVL (SystemVerilog, SystemC), HDL (Verilog), C/C++ and scripts (perl, shell). Familiarly with Industry Standard Verification Methodologies e.g UVM
- Prior experience in verification/design of Image/Video Processing, Video/Audio Interface (HDMI, DisplayPort etc.) Video Decode/Encode and/or compression/de-compression IPs
- Hands on experience in Industry standard simulation & debugging tools i.e. Questa/VCS and Verdi etc
- Working experience and good understanding of state of art verification technologies i.e. coverage and assertion based, formal verification and HW assisted verification
9
Responsibilities For Staff Digital Design & Verification Engineer Resume
- Build test bench and create testcase to ensure maximum coverage
- Explore advanced verification methodology, optimize the verification process/environment to improve efficiency and quality
- Support DV manager to do the verification quality control and sign-off the DV task
- Familiarity with the Arm AMBA specifications or other bus protocols
- Excellent presentation, interpersonal and communication skills with a demonstrated ability to communicate complex technical concepts with different audiences, including technical team members, senior partners and customers
- Have championed at C/ASM testing, functional/power/performance, HVL verification and successfully lead 2 (at least) projects with
- SystemVerilog modeling for analog and mixed-signal blocks
10
Responsibilities For Staff Asic / Fpga Verification Engineer Resume
- Coverage metrics definition and coverage model development based on marketing and design specifications
- High-level modeling and/or test environments of CPU cores, core components and systems
- Be familiar with FPGA debug
- Be familiar with SoC peripherals such as USB, PCIE, SPI, UART
- Hands-on Experience in development of test bench architecture, test cases, functional & code coverage, running regressions and debugging tests; Ability to contribute to verification tasks with minimal guidance is required
- Optionally line management of small team
- Directed test expertise with some UVM and assertion generation
- Optional line management of small team
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