Design Verification Engineer Resume Sample
Zander Beahan
75404 Quitzon Views,
Dallas,
TX
+1 (555) 943 1149
Work Experience
Senior Test Chip Design & Verification Engineer
02/2018
-
PRESENT
Philadelphia, PA
- Strong understanding of logic design and computer architecture
- Looking at the RTL to find functional bugs
- Working with the RTL team to fix the bugs, reading Specs and developing test plans, functional coverage points, monitors, scoreboards, sequencers, and sequences, which utilize scripts, System Verilog/UVM, some C++, DFT, and methodologies to increase the rate with which bugs are found and resolved
- Creative and innovator and thinker who loves technical problems and detail-oriented tasks
- Experience with process and methodology improvements to enhance verification productivity
- Predict the scope of verification tasks and set priorities for effective verification
- Perform SOC/IP level functional verification
- Execute test plans, block and chip level test benches using SystemVerlilog (VMM/UMV) based methodology; achieve complete coverage to ensure first working silicon
Design Verification Engineer
09/2011
-
10/2017
San Francisco, CA
- Preparing and maintaining of specific documents and data like functional specifications, safety analysis reports, and safety verification plans
- Good understanding of ASIC design flow and DV methodologies
- Good understanding of ARM CPU v7/v8 architecture and AMBA specifications (AXI, ACE, AHB, APB)
- Experience in verifying design at block level and system level using constraint random environment
- Expert in assembly, C, system Verilog, OVM/UVM
- Expert in System Verilog Assertions, Code/functional coverage
- Exposure in Formal verification
- Debugging functional errors in the RTL model, using simulation tools, debug tools and based on in-depth understanding of the architecture and RTL design
IC Design Verification Engineer, Entry Level
01/2006
-
08/2011
Boston, MA
- Acquiring a deep understand of the architecture which combines enormous computational capability, high-bandwidth fabric, coherent memory hierarchy and flexible I/O solutions
- Creating state-of-the-art validation environments and infrastructure, including drivers, checkers, monitors, exercisers, etc
- Applying verification best practices – planning, coding, random and focused testing, debugging, coverage analysis, etc
- Industry experience in the following areas
- Perform SOC/IP level functional verification using SystemVerilog/UVM
- Independently root cause functional verification failure
- Executing safety analysis (Failure Mode Effect and Diagnostic Analysis, Fault Tree Analysis) on PSG IP products
- Identifying and characterizing mitigation measures for preventing or detecting faults potentially affecting integrated circuits
- Executing fault injection testing to verify the performance of such mitigation measures
Education
Oklahoma State University - Tulsa
2002 - 2006
Engineer's Degree in Electrical Engineering
Professional Skills
- Good written and verbal communication skills. Strong communication skills is required
- Self-motivation, strong problem solving and excellent verbal/written communication skills
- Besides mastering the mentioned technical skills we expect evident project team spirit, engagement, communication skills and clear orientation to results
- Strong debug skills and experience with debug tools such as DVE/Verdi
- Strong communication skills both written and verbal are essential as is ability to work effectively as part of a team
- Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms
- Strong programming and scripting skills including C/C++/Java/Perl/Python
How to write Design Verification Engineer Resume
Design Verification Engineer role is responsible for programming, software, scripting, english, design, debugging, architecture, languages, debug, perl.
To write great resume for design verification engineer job, your resume must include:
- Your contact information
- Work experience
- Education
- Skill listing
Contact Information For Design Verification Engineer Resume
The section contact information is important in your design verification engineer resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:
- First and last name
- Telephone number
Work Experience in Your Design Verification Engineer Resume
The section work experience is an essential part of your design verification engineer resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous design verification engineer responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular design verification engineer position you're applying to.
The work experience section should be the detailed summary of your latest 3 or 4 positions.
Representative Design Verification Engineer resume experience can include:
- Strong inter-personal, teamwork and communication skills including English fluency
- Excellent problem solving and verbal/written communication skills
- Strong scripting skills in PERL, Python
- At least 3 months experience with high quality scripting Perl or Python and debug skills
- Strong System Verilog, PERL, TCL, and C/C++ programming skills
- Excellent interpersonal skills and the dream to take on diverse challenges
Education on a Design Verification Engineer Resume
Make sure to make education a priority on your design verification engineer resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your design verification engineer experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.
Additional details to include:
- School you graduated from
- Major/ minor
- Year of graduation
- Location of school
These are the four additional pieces of information you should mention when listing your education on your resume.
Professional Skills in Design Verification Engineer Resume
When listing skills on your design verification engineer resume, remember always to be honest about your level of ability. Include the Skills section after experience.
Present the most important skills in your resume, there's a list of typical design verification engineer skills:
- Strong analytical, and problem solving skills as well as debugging skills
- Good communication skills, both oral and written, and strong listening ability
- Solid problem solving and trouble shooting skills
- Strong software skills including C++ programming
- Good debugging skills in bug triage and analysis, and simulation
- Team player, with excellent debugging skills
List of Typical Experience For a Design Verification Engineer Resume
1
Experience For Asic Design Verification Engineer Resume
- Strong communication skills and the ability to work with a team spread across different geography sites
- Strong communication skills with the ability to convey complex technical concepts to other verification peers both verbally and written
- Good communication skills and cross-functional teamwork
- With Masters) or 8+ years (with Bachelors) of proven verification experience on large ASIC development projects in a hardware development setting
- Self-motivated, good communicator, quick learner and good team player
- Design system level validation environments at multiple levels of abstraction i.e. analog parametrics, system level validation and device emulation
- 6) Able to learn independently and acquire new skills required for the job
2
Experience For MTS Design Verification Engineer Resume
- Multiprocessing microarchitecture experience
- Experience in RTL coding using VHDL or Verilog. VHDL is desirable
- Good knowledge in languages relevant to the ASIC verification process including Verilog, SystemVerilog, Unix Scripting, Perl, Python, and C++
- Experience designing and testing modern electronics hardware at component, board, and system levels
- BSEE/MSEE and 8+ years' experience in Verification and/or Design including the following
- Very good understanding of digital design flow
- Very strong background in C/C++/OOO coding techniques
- Experience working with Cadence NCSIM, Synopsys VCS or equivalent
- Experience with perl, python or similar scripting language
3
Experience For Fpga Design / Verification Engineer Resume
- Compose test plan following design specs and validation vectors to ensure functional
- Experience in electro acoustic system engineering
- Experience with amplifier design and testing
- Experience in Unix/Linux OS, and scripting language like perl
- Experience in leading a small team of engineers
- Experience in function verification and timing analysis
- Experience using SystemVerilog, VMM or UVM
- Or more of practical semiconductor design verification experience including System Verilog, UVM, assertions and coverage driven verification
- Previously experience of working in an AS9100 certified environment
4
Experience For Senior Test Chip Design & Verification Engineer Resume
- Good knowledge on Verilog RTL coding
- Good knowledge on programming language such as C++
- Good knowledge on scripting language such as TCL and PERL
- · 10 years or more of practical semiconductor design verification experience including System Verilog, UVM and coverage driven verification
- Experience working in the hardware industry
- BS or MS in Electrical Engineering, Computer Science or equivalent experience
5
Experience For Senior Medical Device Design Verification Engineer Resume
- BS in Electrical Engineering or Computer Science or equivalent experience
- BS Electrical Engineering/Computer Science or equivalent experience
- Experience using industry standard tools and adaptability to utilize home grown tools
- Development of verification plans that identify and prioritize verification requirements based on architecture, design and marketing documents
- Experience developing scalable and portable test-benches
- Or more of practical semiconductor design verification experience using System Verilog and UVM
6
Experience For Digital Design & Verification Engineer Resume
- Experience with developing automated test systems
- Experience in programming such as VB.NET
- Good understanding of digital hardware architecture and design concepts (RTL)
- Strong OOP expertise in C++, Python or similar programming language
- Experience in developing state-of-the-art verification environments
7
Experience For Asic Design / Verification Engineer Resume
- Experience in developing RTL verification plans
- Experience in the development, assessment, and refinement of RTL design to target power, performance, area and timing goals
- Experience working with different functional teams such as emulation, firmware, hardware
- Experience in development, assessment, and refinement of RTL design to target power, performance, area and timing goals
- 3+ yrs. of working experience in UVM
- Experience developing with C, C++ or Python (2 years+)
- Experienced working with analogue or digital electronics is essential
- Extensive experience with testing tools, automation, and software packages
8
Experience For Design Verification Engineer Specialist Resume
- Experience with Quartus-II or ISE
- Experience with complex ASIC designs and/or verification
- Experience on UVM verification methodology, and formal verification method
- Experience in Verilog code design and verification
- Significant amount of experience in a verification or development role
- Interfaces with Architecture, ASIC, and Validation teams through the product technology development phase
- Experience in the area of processor / SoC verification
- Hands-on resolution of problems and priority calls
- Experience with industry standard protocols and interfaces such as AXI4, ACE-lite and/or PIPE
9
Experience For IC Design Verification Engineer, Entry Level Resume
- Good knowledge on digital logic and circuit design
- Good knowledge on logic verification methodology
- Good knowledge on SystemVerilog object-oriented language
- Ystem Verilog OVM/UVM DV experience
- Experience with assertions (SVA) or others
10
Experience For SoC Design & Verification Engineer Resume
- Experience with digital ASIC architecture and µArchitecture
- Experience with digital ASICs design flows
- The plan encompasses functional, system level and hardware verification and validation perspectives
- Review verification and validation results against the coverage goals
- Experience submitting jobs through network compute farms
- Hands-on experience with analog assertion checks
- BS in EE, CS or equivalent experience
List of Typical Skills For a Design Verification Engineer Resume
1
Skills For Asic Design Verification Engineer Resume
- Attention to details, and excellent verbal and written communication skills
- Strong skills in documentation: test reports, presentations and procedures
- Self-motivated, excellent communication skills and ability to excel in a team environment across the globe
- Seeking the following skills
- Applying debug skills and root causing complex HW/SW issues
2
Skills For MTS Design Verification Engineer Resume
- Confirmed software engineering skills including understanding of object-oriented programming, data structures, and algorithms
- Experience creating and executing coverage-driven validation plans
- Experience using advanced system design and validation methodologies and technologies, such as FPGA prototyping, emulation, simulation and co-emulation
- Design verification experience with a proven track record of successfully verifying and delivering complex ASICs, FPGAs or SoC
- Advanced skills in various programming languages including Verilog, System Verilog, C, C++, PERL, TCL
- Co-op/Internship demonstrating verification experience on large ASIC development projects or equivalent embedded programming experience an asset
- Demonstrate experience working with Mentor's Calibre DRC, LVS, LVS-ADP
3
Skills For Fpga Design / Verification Engineer Resume
- Demonstrate working experience with Synopsys ICV and Mentor's Calibre tool
- Experience with Wi-Fi or other networking protocols strongly desired
- Industry experience, 4+ years experience required in the following areas
- Lab skills including emulation with combined FPGA and analog environments
- Experience in medical devices with FDA’s QSR, MDD, and general risk management is strongly encouraged
- Experience in RTL design with System Verilog/Verilog is a strong pluso
- Leadership skills, self-driven and highly motivated individual
- Perl, Python, tcl, C, C++ or SystemC skills
- Intelligence, enthusiasm, and a solid work ethic are valued more than any skill
4
Skills For Senior Test Chip Design & Verification Engineer Resume
- Language skills – Verilog, C++, System Verilog/Vera/Specman, Synthesis, Lint
- Working experience needs to demonstrate the technical expertise in successful completion of multiple ASIC/FPGA projects
- Have excellent knowledge and experience of ASIC design verification flows and methodologies
- Able to learn independently and acquire new skills required for the job
- Create comprehensive verification and validation plan based on IP architecture specifications and carry out all the IP validation tasks
- Develop, participate and review validation code for efficiency/coverage and drive any paradigm shifts needed in validation execution
- Programming and scripting experience, C++, TCL, and Perl
- Working experience with Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement
5
Skills For Senior Medical Device Design Verification Engineer Resume
- Working experience with Design Verification Tools and Process flows with leading edge ASIC technologies
- Working DDR knowledge with experience in verifying DDR PHY/Controller in both Pre and Post Silicon
- Working experience in IP / SoC verification
- Working experience in UNIX software environment
- Creates test plans for RTL validation, defining and running IP simulation models, and finding and implementing corrective measures for failing RTL tests
- Create test plans for RTL validation, defining and running IP simulation models, and finding and implementing corrective measures for failing RTL tests
- Experience working on timing constraints, synthesis, power and area optimizations, UPF, voltage scaling, and static timing analysis
6
Skills For Digital Design & Verification Engineer Resume
- Experience working with timing constraints, synthesis, power and area optimizations, UPF, voltage scaling, DFT insertion, and static timing analysis
- Experience in digital design & verification Test planning, problem solving, debug, adversarial testing
- Experience characterizing imaging systems at the sensor and camera system level including optical measurement and measurement automation
- Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage
- Experience in writing feature based test plans and implementing such test plans using one of the methodologies listed above
- Experience running regressions, debugging test failures and achieving test plan targets
7
Skills For Asic Design / Verification Engineer Resume
- Experience coding RTL and debugging digital designs
- Experience developing test plans and test benches, utilizing directed and constrained random techniques, preferably in a UVM environment
- Solid understanding of Object Oriented Programming (OOP) Principles
- Interconnect or Multiprocessing microarchitecture experience including knowledge of bus protocols (eg AMBA5 CHI, AMBA4 ACE or AXI)
- Experience developing protocol checkers using System Verilog Assertions
8
Skills For Design Verification Engineer Specialist Resume
- Experience running and debugging gate level simulations
- Experienced designing test suites and executing
- Experience in object oriented programming and/or scripting C++, Perl, Python or others
- Experience of articulating customer requirements and specifying them in SoC features
- Hands-on experience in designing VLSI components, integrated circuitry, architectures and developing algorithms
- Experience coding RTL and debugging high performance complex digital designs
- C, C++ coding, debugging experience
- C, C++ coding and debugging experience
- Experience in all aspects of pre-silicon functional verification, including planning, debug, testbench design and coverage closure
9
Skills For IC Design Verification Engineer, Entry Level Resume
- Experience in creating and refining SoC- and IP-level architecture
- Strong programming and scripting language capability
- Design bug reporting and fix validation
- Experience in Tcl, Perl and bash scripting
- Experience of integration with mixed signal electronics, adhering to analogue performance specifications
- Experience in all aspects of PCB design and surface mount manufacturing
10
Skills For SoC Design & Verification Engineer Resume
- Experience in Python / GIT / Jenkins working in a regulated environment
- Experience with Perl, Python, Unix scripting
- Industry experience in the following areas
- Good understanding of abstraction techniques and formal verification techniques
- Experience writing scripts in Perl, Python, or TCL
- Extensive experience in functional modeling of industry/internal interfaces with SystemVerilog/ C++
- Experience in developing coverage-driven verification test plans
- To architect and validate ARM CPU based test chips used for silicon process proving
- Experience verifying devices with AMBA Bus protocols
List of Typical Responsibilities For a Design Verification Engineer Resume
1
Responsibilities For Asic Design Verification Engineer Resume
- Experience in Cellular WiMax, LTE, and/or other Physical layer WiFi, Ethernet technologies and embedded SW & HW design is a strong pluso
- Fluent English language is mandatory, German communication skills are desired
- Compose test plan following design specs and validation vectors to ensure functional completeness
- Experience in one of the following: UVM/OVM/VMM, and constrained-random simulation
- RTL coding experience
- Hands-on experience with Block level and System level tests writing for FPGA / ASIC designs
- At least 2+years of relevant ASIC DV experience
- Relevant ASIC DV experience
2
Responsibilities For MTS Design Verification Engineer Resume
- Above 2 years of ASIC design/verification experience
- Experience with micro speaker and digital microphone design
- Industry experience in Digital Design
- Industry experience in System Verilog OVM/UVM DV
- Experience in consumer electronics
- Research or industry experience in Digital Design
- Research or industry experience in System Verilog
- System Verilog OVM/UVM DV experience
3
Responsibilities For Fpga Design / Verification Engineer Resume
- Ystem Verilog OVM/UVM DV experience
- Nice to have experience in non-volatile memory designs such as NAND flash
- Experience in the area of processor / SoC verification
- Excellent knowledge with AMBA interfaces (i.e AXI, AHB) and ARM Trustzone
- Good knowledge of ARM Microprocessor architecture
4
Responsibilities For Senior Test Chip Design & Verification Engineer Resume
- Experience with serial protocols such as PCIe or USB
- Experience with mixed signal verification methodology for IPs such as PHYs, PLLs etc
- In lieu of UVM knowledge, C/C++ experienced level knowledge
- Experience in design verification with UVM and constrained random, coverage based verification approaches
- MSEE with 3+ years of industry experience
- Define and execute verification test strategies to validate product functionality
- Contribute to FMEA and DOE in the design phase and test alpha samples for performance validation
- BE/MTECH with 5 to 8 years of experience in SOC/IP Verification
5
Responsibilities For Senior Medical Device Design Verification Engineer Resume
- Promote and demonstrate the ARM core beliefs and behaviors
- Experience in digital design & verification
- Cellular Wireless (LTE/UMTS) or 802.11/Wi-Fi Chipset Industry experience with verified Data Path Blocks (FFT's, Filters, Demodulator, Decoder, etc.)
- Experience with Hardware Verification Languages (HVL) such as SystemVerilog (UVM), Vera, SystemC, etc.
- Plan and track validation for complex SoC’s
6
Responsibilities For Digital Design & Verification Engineer Resume
- Experience with computer architecture
- PLL, serdes and/or PHY experience
- ARM, memory subsystem experience
- Good knowledge of EMI/EMC requirements and electronic interfaces
- Experience background in PCIe or Ethernet protocols
- Experience with HW/SW debug
7
Responsibilities For Asic Design / Verification Engineer Resume
- Experience with 3rd party verification IPs
- Hands-on experience with SystemVerilog UVM
- Relevant experience in digital design and/or verification
- Strong background in PCIe or Ethernet protocols
- Experience in formal verification and analysis of pipelined microarchitectures and coherent memory systems
- Experience with HDL’s such as Verilog, SystemVerilog, and temporal logic assertion languages such as SVA
8
Responsibilities For Design Verification Engineer Specialist Resume
- In depth knowledge/experience of System Verilog UVM
- Experience in coverage points coding, SV test writing & debug testbench
- Directly related industry experience in ASIC / SoC Verification
- Experience developing verification collateral in Verilog, System Verilog and UVM
- Experience (at least)in design verification
9
Responsibilities For IC Design Verification Engineer, Entry Level Resume
- Previous experience in specification, creation, and debug of SystemVerilog/UVM constrained-random testbenches
- M.Tech/M.S with 3-5 years of experience in digital design / design verification
- Hands-on experience with optical measurement equipment e.g. spectrometer, gloss meter, common electrical measurement tools, etc
- Relevant experience in digital design and/or verification
- 5+ yrs. of ASIC Verification experience
- MSEE/CS with up to 3 years of experience
- In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification
- Develop directed and random verification tests to validate block and IP functionality
- Experience with testbench design and implementation
10
Responsibilities For SoC Design & Verification Engineer Resume
- Experience with flows and tools for VLSI logic design and/or functional verification
- Experience in verification lead position
- Experience in high level Object Oriented test bench environments such as VMM/UVM
- BSCE/BSEE and 2+ years of experience or MSCE/MSEE desired
- Experience with Verilog, Perl, and logic simulation is a requirement
- MS and 2+ yrs or BS and 5+ yrs of Functional Verification experience
- Equivalent industry or research experience
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