Senior Design Verification Engineer Resume Sample
Jackie Lebsack
2260 Moen Fields,
Dallas,
TX
+1 (555) 947 9969
Work Experience
Senior Design Verification Engineer
05/2016
-
PRESENT
Detroit, MI
- Experience developing low level and/embedded software
- Experience with assembly language programming (x86 or ARM)
- Fluent in C and C++ and one or more scripting languages
- In-depth knowledge of x86/PowerPC/Arm Processor Architecture (ISA & micro-architecture)
- Experience in validation methodologies, post-silicon test processes and methods and in debugging microprocessor issues using JTAG based debugging tools and traces
- Experience in development of tools which help in stressing different features of a processor
- Experience debugging complex system level problems including but not limited to silicon and/or platform issues
SSD Senior Design Verification Engineer
06/2012
-
03/2016
Los Angeles, CA
- Great communicator with experience in providing technical leadership within a team of engineers
- Developing detailed test plans to test Cavium’s next generation multicore SoC processors
- Building test-benches in System Verilog using UVM flow
- Assisting with designing test-bench architecture
- Coding architecture reference models in C/C++
- Ensuring complete code and functional coverage of the design
- Identify Register Transfer level (RTL) bugs, potentially correct RTL; and,
Senior Design / Verification Engineer
07/2007
-
05/2012
Phoenix, AZ
- Working closely with Design Engineers and Chip Architects to achieve required results, including conduct performance analysis
- Expertise in HVL and HDL (SystemVerilog and / or Verilog)
- Design world class hardware and software
- Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architect
- Create and enhance constrained-random verification environments using SystemVerilog and UVM
- Knowledge of industry standard interfaces, deep understanding of Verilog, Verilog simulator and debug
- Post Deployment Sustenance Responsibilities
- Be capable of defining and executing system-level tests to help validate system specifications
Education
Brigham Young University
2003 - 2007
Engineer's Degree in Electronics
Professional Skills
- Good development skills in C/C++ design and coding, with strong debugging skills
- Creative problem solving skills, attention to detail, and good coding skills are required
- Fluency in English and excellent communication skills to enable efficient working on multi-site projects
- Strong skills in Assertion Based Verification using PSL/SVA
- Strong scripting skills Perl/Ruby/Tcl/Python
- Excellent oral and written communication skills with ability to motivate, mentor and develop a world-class team
- Excellent skills in a modern verification methodology such as UVM/OVM
How to write Senior Design Verification Engineer Resume
Senior Design Verification Engineer role is responsible for design, programming, scripting, java, languages, digital, assembly, reporting, architecture, automation.
To write great resume for senior design verification engineer job, your resume must include:
- Your contact information
- Work experience
- Education
- Skill listing
Contact Information For Senior Design Verification Engineer Resume
The section contact information is important in your senior design verification engineer resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:
- First and last name
- Telephone number
Work Experience in Your Senior Design Verification Engineer Resume
The section work experience is an essential part of your senior design verification engineer resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous senior design verification engineer responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular senior design verification engineer position you're applying to.
The work experience section should be the detailed summary of your latest 3 or 4 positions.
Representative Senior Design Verification Engineer resume experience can include:
- Good verbal and written communication skills to work effectively with teams spread geographically
- 5+years experience of strong protocol expertise and implementation experience of PCI-Express
- Design verification experience with a proven track record of successfully verifying and delivering complex ASICs, FPGAs or SOC
- Prior experience in integrating Verification IPs (VIP) & UVC in verification environment
- Prior experience with verifying snoop filters and directory based cache structures
- Prior experience in verifying Multichip coherency
Education on a Senior Design Verification Engineer Resume
Make sure to make education a priority on your senior design verification engineer resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your senior design verification engineer experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.
Additional details to include:
- School you graduated from
- Major/ minor
- Year of graduation
- Location of school
These are the four additional pieces of information you should mention when listing your education on your resume.
Professional Skills in Senior Design Verification Engineer Resume
When listing skills on your senior design verification engineer resume, remember always to be honest about your level of ability. Include the Skills section after experience.
Present the most important skills in your resume, there's a list of typical senior design verification engineer skills:
- Good debugging skills and working knowledge of scripting using perl or python
- Understanding and prior experience in verifying cache coherent protocols
- Coding skills in Perl, TCL, Shell scripts, Makefile
- Work experience in a similar position designing, verifying, and validating complex hardware systems
- Prior experience in working on caching protocols such as ACE and CHI
- Prior experience in bringing up gate level simulation and debugging issues
List of Typical Experience For a Senior Design Verification Engineer Resume
1
Experience For SSD Senior Design Verification Engineer Resume
- Collaborate with other technical contributors on system validation and integration testing with hardware
- Experience with Altera and Xilinx FPGA synthesis and development environment is an advantage
- Adept in programming and/or scripting with C++
- Master or foreign equivalent in Electrical Engineering, Computer Engineering, Computer Science or related field
- Capable of building block and system level testbench from scratch using system Verilog, UVM constrained random coverage driven concepts
- Testplan development and testplan execution (test writing) including scoreboard development
- Automation using scripting languages (Python or Perl); and,
2
Experience For Senior Design / Verification Engineer Resume
- TestBench Development in SystemVerilog targeting complete functinality coverage
- RTL and Firmware debugging
- Debug failures in simulation and collaborate with designers in root-causing failures
- Investigate methods to improve analog behavioral modeling for functional verification
- Verification of complex digital blocks/ SoCs/High Speed signal processing products
- Execute test procedures and debug proof of concepts or early engineering designs
- Ownership of testbench development, including stimulus, checkers, assertions and coverage
3
Experience For Senior. / Design Verification Engineer Resume
- Deep knowledge of one of the scripting languages: Python, Perl, TCL
- System level verification using FPGA and Palladium platforms
- Knowledge of any of the following protocols: USB, MIPI, NAND Flash memories / SDIO, SD or eMMC standards
- Testplan execution (test writing)
- Diligent, willing to take initiative, and able to handle assignments with minimal supervision
- Familiarity with caching protocols such as MESI, MOSEI
- Expertise in scripting languages, TCL, PERL, ARM processor bus protocol such as AHB, AXI is highly desired
- Digital Video processing and Broadcast systems like HDMI/HDCP/DP knowledge is highly desired
4
Experience For Senior Design & Verification Engineer Resume
- Lead and oversee design verification efforts of a cluster of blocks
- Full-chip functional verification on Micron’s non-volatile memory design projects
- Behavioral model development of Micron’s non-volatile memory
- Technical support to verification team members in Micron’s China and other global offices
- Develop test environment, test plan and test cases based on FPGA and product specification. Require to execute test cases, debug, resolve issues to meet full features in functional requirements
- Strong experience with Verilog and development of system Verilog test benches for full chip test bench environments with Cadence IES, Questasim to test full FPGA chip
5
Experience For Senior Design Verification Engineer, CSM Resume
- Proficient developing directed tests and constraint random tests(UVM test suite) environment and a strong understanding of system Verilog assertions
- Exposure to integration and debugging tools, such as oscilloscope and logic analyzers is an advantage
- Self-driven and able to work independently in a fast moving dynamic environment
- Familiarity with verification of common interfaces (PCI-Express, DDR3/4, I2C, SPI, RS232, MDIO, XAUI)
- The verification engineer is responsible for driving the successful verification of non-volatile memory modules from RTL and/or Firmware development through final releases
- Determine applicability of tools for project success
6
Experience For Senior Design Verification Engineer Resume
- Ensure verification coverage, regression metrics and appropriate reviews are met before each delivery
- Drive debug and closure of regression signatures using waveform viewer and output files; and collaborate with the RTL designers and testbench owners to fix bugs
- Develop quality, timely and cost effective solutions independently. Contribute to testbench and/or IT infrastructure, helping to build a reliable, scalable, and flexible verification environment
- Coursework or experience in analog and/or mixed signal circuit design
- Develop/Enhance UVM testbench components like test-cases, monitors, scoreboards, sequencers, and sequences for new features
- Review design document and develop verification strategies for SerDes designs
- Develop verification plans and create block and chip level verification environments
- Create testcases to meet functional and code coverage goals
7
Experience For SSD Senior Design Verification Engineer Resume
- Define testplan, tests and verification methodology for block and chiplevel verification
- Architect the testbench and develop in UVM or Formal based verification approaches. Integrate the block testbench at chiplevel UVM environment and verify integration
- Work with design team in generating test-plans and closure of code and functional coverage. The job also needs continuous interaction with analog co-sim and firmware team in enabling toplevel chip verification aspects
- Experience in design verification with UVM and constrained random, coverage based verification approaches
- Good Knowledge in Processor/SoC architecture, DSP fundamentals
- Experience with functional test generation in C programming language on ARM processors
- Support post-silicon verification activities of the products working with product evaluation and applications engineering team
8
Experience For Senior Design / Verification Engineer Resume
- Supports Applications Engineering in debugging customer issues
- Proficient in one of the following: UVM/OVM/VMM
- Support of Tier 1 high volume consumer electronics manufacturing test systems
- Exposure to industry standard verification tools is required
- Technically mentor 1-2 junior engineers
- Develop and maintain UVM and C based test benches to test our nextgeneration SSD Controllers
- Develop test cases in C/C++ to verify functional operation of that the system level
- BSEE or MSEE with 4+ years of experience in SoC/ASIC verification in Verilog, SystemVerilog and UVM test benches, with an emphasis on the development of UVM based SoC level test benches
- Creates verification plans at the block level
9
Experience For Senior. / Design Verification Engineer Resume
- Understands protocols and standards associated with products
- Collaborates with program management to verify that components meet technical specifications and quality requirements (e.g., power efficiency, area efficiency, ease of use)
- Collaborates with other hardware and software groups to ensure effective component integration within the larger system
- Troubleshoots component blocks as required to ensure milestone achievement and production-ready integration (e.g., specifications, performance, standards)
- Manages regression suites for products, and contributes to the tool flow
- Acts on verification test data to ensure seamless component integration, device manufacturability, and sign-off acceptability if applicable (e.g., customer sample feedback, iterative tape-out production turns involving 3rd parties)
- Create and/or enhance test benches by developing a thorough understanding of the design under test
- When required, creates environment and infrastructure to test designs in a HW verification environment, and running test scenarios
- Build reusable DV infrastructure components for module and top level environments
10
Experience For Senior Design & Verification Engineer Resume
- Define and document test plans for module/block level (IP) and system level verification
- Identify and write coverage measures for stimulus and corner-cases
- Define, implement, automate, and execute regression tests
- Working knowledge of functional verification including: test plan development, bus functional models, random stimulus generation, functional coverage, monitors, checkers, scoreboards, and sequencers
- Deep knowledge of Verilog and System Verilog
- Develop innovative test methods to ensure robust MTE hardware qualification using automation, stress testing, performance, design margin, and corner case test variations
- Proven experience in mixed signal verification methodology for IPs such as PHYs, PLLs etc
List of Typical Skills For a Senior Design Verification Engineer Resume
1
Skills For SSD Senior Design Verification Engineer Resume
- Prior experience in high speed serial protocols such PCIE and 10G Ethernet
- Prior experience in verification of cache sub systems in processors and/or cache coherent interconnect such as CCI400
- Prior experience with coherent interfaces like IBM CAPI (Coherent Accelerator Processor Interface)
- Prior experience with protocols such as AXI, APB, AHB etc
- Experience with hardware validation of complex digital systems
- Working closely with design engineering teams to resolve failure issues and align priorities to achieve on-time delivery
2
Skills For Senior Design / Verification Engineer Resume
- Understanding of FPGA architecture and good logic design fundamentals
- Supports Test Engineering or customer verification engineering teams in the setting up of valid test verification criteria and plans
- Experience in Verilog modeling of circuit behavior, Verilog/logic simulations and scripting languages
- Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
- Demonstrated track record in developing/verifying hardware IP systems as well as deep knowledge of EDA design processes and tools
- Experience with Object Oriented Programming using SystemVerilog/SystemC or equivalent
- Experience developing Verification Plan including constrained random and directed tests
3
Skills For Senior. / Design Verification Engineer Resume
- Experience in modeling of analog blocks using real/wreal data type
- Experience working with a multi-disciplinary team including support for Test Engineers
- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments and system testing
- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
- Experience developing and executing test plans for IP level and/or SOC level verification
- Experience of working on multi-site projects
- Perl and C/C++ programming language experience desirable
- Experience using coverage tools for Code Coverage, Functional Coverage
4
Skills For Senior Design & Verification Engineer Resume
- Experience working across boundaries of mixed signal ICs
- Good understanding of different phases of ASIC and/or full custom chip development is required
- Or more of practical semiconductor design verification experience including System Verilog, UVM, assertions and coverage driven verification
- Experience with industry standard tools and scripting languages (Python or Perl) for automation
- Experience defining verification plan, test plan and coverage plan
- Experience in hardware bring-up, characterization and failure root cause analysis
- Experience supporting complex automated test system design and characterization
- Experience as a technical lead mentoring other engineers
- Strong understanding of SystemVerilog & Assertions
5
Skills For Senior Design Verification Engineer, CSM Resume
- A proven track record of shipping quality products on time
- Experience with formal property checking tools such as Cadence (IEV), Jasper and
- Strong RTL coding and familiar with front-end design flow
- Experience on synthesis, timing analysis and formal verification
- Experience with silicon bringup, emulation, or FPGA prototyping
- Experience in leading Design Verification projects
- Or more of practical semiconductor design verification experience using System Verilog and UVM
6
Skills For Senior Design Verification Engineer Resume
- Experience using multiple verification platforms: FPGA, emulator, software environments and/or post-silicon
- Impactful experience developing scalable and portable test-benches
- Experience with standard CAD tools for PCBA layout, schematic design and analysis
- Verification experience
- Some digital design experience
- BS / MS with at least 2+ years of experience
- Experience with test bench environments for unit and system level verification
- Design validation environment development in SV/UVM and SV/C
- OOP-based computer language concept and development experiences
7
Skills For SSD Senior Design Verification Engineer Resume
- BSEE with 5+ years or MSEE with 2+ years of relevant experience
- Industry experience in Functional Verification
- Experience with industry standard I/O interfaces
- Excellent verbal and written English communication abilities and technical literacy
- ASIC verification experience
- Experience with testbench design and implementation
8
Skills For Senior Design / Verification Engineer Resume
- Experience in design verification for IP/system level
- Digital IC design and verification experience
- Progressive experience as Design Engineer, ASIC Designer or related occupation
- Progressive experience as a Staff Verification Engineer, Member of Technical Staff, or related occupation
- Progressive experience as Design Verification Engineer, ASIC Engineer, System Engineer or related occupation
- MS + 3 years or BS + 5 years’ experience desired
- Have previous experience with sensors such as gyros, accelerators and cameras
- Experienced with statistical data analysis techniques to identify critical performance metrics and limits
- Five to fifteen years of experience in large scale logic design verification projects
9
Skills For Senior. / Design Verification Engineer Resume
- Analyzing and debugging the failures in simulation using tools including one of the following: Synopsys VCS, Cadence IES or Mentor Modelsim/Questa
- Architecting verification environments using advanced verification concepts including one of the following: UVM, OVM or VMM
- Outstanding technical problem solving and debugging ability
- Understanding of caching protocols such as MESI,MOSEI and concepts like snoop filters
- Understanding of ARM architecture and assembly language programming
- Understanding and knowledge of object oriented programming concepts
- Architecting verification environments using advanced verification concepts such as UVM, OVM or VMM
- Working on applying Formal Based Verification to verify designs
- Working knowledge of SoC architecture and design, including CPU, GPU, peripherals, bus protocols, NoC, etc
10
Skills For Senior Design & Verification Engineer Resume
- Understanding of FPGA architecture
- Knowing UVM/OVM is an added advantage
- Coverage writing (including coverpoints, and crosses), coverage collection and improving coverage of the design under test
- A passion learning new technology, solving complex problems, and delivering on quality
- Support the verification planning process defining verification requirements
- Adept in programming and/or scripting (C++, Perl and others)
List of Typical Responsibilities For a Senior Design Verification Engineer Resume
1
Responsibilities For SSD Senior Design Verification Engineer Resume
- Fluent using industry standard verification methodologies
- Track record of defining verification methodologies
- Drive verification closure by closing regressions, functional bugs and code and functional coverage
- Proficient with scripting languages (Python or Perl) for automation
- An MS/BS in EE, Computer Engineering or equivalent
2
Responsibilities For Senior Design / Verification Engineer Resume
- High tolerance for ambiguity working through incubation to actual product definition to execution
- Perform statistical analysis on MTE test systems
- Provide detailed analysis and informative summaries of test data
- Use statistical data analysis techniques to help set product test requirements and limits
- Deep knowledge of System Verilog test-bench language and UVM
- Significant experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
- Strong knowledge of formal verification methodology
- Deep knowledge with serial protocols such as PCIe or USB
- In lieu of UVM knowledge, C/C++ expert level knowledge
3
Responsibilities For Senior. / Design Verification Engineer Resume
- Exposure to formal verification methodologies
- Solid understanding of state-of-the-art verification methodology, proficiency in design/verification language such as VHDL/Verilog and System Verilog or other verification language
- Familiar with assertion based verification
- Technical knowledge/skills include general concept on video system, familiar with various bus protocols, scripting skills and automation tools to facilitate state-of-the-art verification of digital IP cores
- Familiar with industrial video standards and professional video test equipment
- Advanced knowledge of CPU & SOC architecture/design & in-depth knowledge of verification flow. Experience with low-level programming of complex computer systems in C/C++/assembly
- Knowledge of industry standard interfaces, good understanding of Verilog, Verilog simulator and debug. Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
4
Responsibilities For Senior Design & Verification Engineer Resume
- Through knowledge of verification methodologies like UVM, VMM etc
- Design for verification (assertion based design strategies, code coverage, functional
- Self-motivated personality and a team player
- AXI3, AXI4 Interface verification, AXI Crossbar switch verification
- Familiarity with power and performance concepts
- Design verification at RTL/Gate level, coverage analysis and coverage improvement, at block and Chip level
5
Responsibilities For Senior Design Verification Engineer, CSM Resume
- Develop test cases to verify functional operation
- Familiarity with DDR/LPDDR interfaces
- Own verification of sections and features of new design IP
- Creation of configurable SV UVM testbenches
- Knowledge of System Verilog and SV assertions
6
Responsibilities For Senior Design Verification Engineer Resume
- Familiar with SystemVerilog/C++
- Metric Driven Verification
- Low Power Verification
- Of advantage would be
- Knowledge of System Verilog UVM
- Knowledge of assertion based formal verification
- Knowledge of perl or python
- Knowledge of Statistical Process Controls (SPC) & Six Sigma
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